In high-speed data processing systems, it is often necessary to buffer data streaming between functional elements of a system. In cases where the data stream needs to arrive at its destination in the same order in which it was transmitted, a First In, First Out (FIFO) buffer is typically employed. A FIFO buffer is a type of memory that stores data serially, where the first data element read is the first data element that was stored. A FIFO buffer has an input port and an output port and can store a finite number of data items. The number of data items a FIFO buffer can store is known as the “depth.” The depth of a typical FIFO buffer is generally a power of two. Input port and output port flag signals are provided by the FIFO buffer and are used to facilitate flow control of the data stream so that the FIFO buffer is not written when full or read when empty.
Typically, FIFO buffers are implemented as an addressable array of data storage registers with a write pointer and a read pointer. The input port references the write pointer to address the next available unwritten data storage register of the array and the output port references the read pointer to address the next unread data storage register of the array. The read and write pointers are initially both at the first memory location when the FIFO buffer queue is empty (as used herein, the terms “register” and “memory location” are used interchangeably). As memory locations are written, the write pointer moves to the next memory location to be written. Likewise, as memory locations are read, the read pointer moves to the next memory location to be read. A multiplexer and a counter are used to control the pointers. Utilizing a multiplexer and a counter creates additional combinational logic. This combination logic creates propagation delays, slowing down the buffer.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art for a faster FIFO buffer which can be of any depth.